Advancing European HPC: Lessons from Porting Scientific Codes to RISC-V

On April 29, CEEC hosted our latest  webinar exploring a key question for Europe’s digital future: how ready are our scientific applications for emerging European hardware?

As efforts around European chip sovereignty accelerate, porting and evaluating applications on new architectures is becoming essential. In this session, CEEC experts shared hands-on experience working with long-vector RISC-V accelerators developed through European initiatives such as the European Processor Initiative (EPI) and EUPILOT.

The webinar combined technical insight with practical guidance. After introducing the hardware landscape and the role of co-design between application developers and hardware teams, the speakers walked through real-world examples from CEEC applications, including Sod2D and waLBerla. These case studies highlighted both the opportunities and the challenges of adapting codes to long-vector architectures—from optimization strategies to common performance pitfalls.

A key takeaway: performance portability is not automatic. Successfully targeting novel architectures requires deliberate code adaptation, careful benchmarking, and new evaluation approaches. The session also demonstrated how Software Development Vehicles can support this process, helping teams systematically assess readiness and improve performance.

With 27 participants from academia and industry across Europe, the discussion extended beyond the presentation. The lively Q&A sparked conversations around future collaborations, underlining the importance of shared expertise as Europe builds its HPC ecosystem.

Watch the webinar recording and explore the slides below to dive deeper into the technical details and lessons learned. Then make sure to register for the upcoming CEEC webinar on VerifiCarlo on May 27th!

As Europe moves toward greater digital sovereignty, initiatives like CEEC’s co-design work with EPI play a crucial role: ensuring that scientific software evolves alongside European hardware—ready to run efficiently on the next generation of supercomputing systems.

Watch the Webinar

Review the Slides