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Introducing Marta Garcia-Gasulla – CEEC CoE
a promotional graphic for the "People of CEEC Series 3" from the Centre of Excellence in Exascale CFD. On the right side, there is a woman with long curly hair, sitting cross-legged and holding a laptop. The laptop has several stickers on it, including ones that say "Mont Blanc" and "OpenMP." Her name, Marta Garcia-Gasulla, is displayed in bold white text on a dark background. On the left side of the image, there is an illustration of a group of five diverse, animated people, appearing cheerful and celebrating. The background is a gradient of blue and green.

Introducing Marta Garcia-Gasulla

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by

Sally K.
in ,

Introducing Marta Garcia-Gasulla

I am Marta Garcia-Gasulla, a team leader at the BSC computer science department.

A woman with long brown wavy HAIR sits cross-legged on the floor in front of a rack of servers - part of Maranostru 4. She has a black laptop with stickers on the lid in her lap. The stickers read "pop", "mont blanc", "OpenMP" and "HPC Bottleneck Chasers". She's wearing a colorful paisley dress and sandals.

I am a computer engineer from the Universitat Politecnica de Cataluna (UPC). I did a master’s in computer architecture and then a Ph.D. in computer architecture at UPC. For my PhD, I developed a runtime library that would improve the load balance of HPC applications: the DLB library. Load balancing is closely related to parallelization. When a piece of software is load balanced, it delegates work in parallel to the greatest number of processors so that work moves as quickly as possible without leaving calculations waiting for hardware to become available while other capable hardware is sitting idle. Dynamic load balancing (DLB) is when a piece of software can reallocate work as hardware becomes available in real-time while a task like a simulation is running.

Towards the end of my PhD, I started working with HPC software that was already being used by scientists and researchers. I realized that there is a gap between the field scientists who use HPC systems to solve a problem (like designing a more fuel-efficient airplane, and computer scientists who are developing the software and hardware for such systems. This was the starting point of the group that I lead: Best Practices for Performance and Portability (BPPP). In the BePPP team, we bridge this gap through the detailed performance analysis of HPC applications to help ensure that the software and hardware meets the needs of its future users.

At CEEC, I would like to help the lighthouse cases efficiently use computational resources, such as future Exascale HPC systems, by using existing features provided by the DLB library and developing new ones when needed.

I will also help the different codes involved in the project to run in the prototypes of the European emerging architectures (EPI and EUPilot projects). With this early analysis, we prepare the software for these architectures and can influence the details of its design.

My ultimate goal in the project is to understand the main performance issues that HPC applications are facing and help them find solutions to these challenges.

The part that I enjoy the most about my work is having contact with the scientists running their simulations, understanding the particularities of their simulations, and further understanding how these particularities affect the performance.