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Flagship scientific applications on a European RISC-V long-vector accelerator: Lessons learned

April 29 @ 2:00 pm – 3:00 pm
A landscape event flyer. Top left, large title text: “Flagship scientific applications on a European RISC-V long-vector accelerator”. Top right, the logo text “CEEC”. Left side shows a large rounded rectangle text box with a curled-paper design on the top-left and bottom-left corners. Inside the box, paragraph text: “Join CEEC and EPI for our experiences and lessons learned when porting applications from CEEC and other Centers of Excellence to the long-vector RISC-V accelerators.” Below it, italic paragraph: “Learn code optimization techniques, common performance pitfalls, and evaluation methods to apply to your own codes on this novel long-vector hardware platform.” Bottom left of the box has three icon-and-text lines: “April 29, 2026”, “14:00 – 15:00 CEST”, “Online”. Right side contains three main graphics. Upper middle is a square chip image labeled “epi” and “EPAC” with smaller text “A0 000010 #2”. Upper right is a bar chart with y-axis label “Speedup” and x-axis label “BLOCK_SIZE” with tick labels “16”, “64”, “128”, “240”, “256”, “512”. The chart legend lists: “Scalar”, “Original vector”, “VEC2”, “IVEC2”, “VEC1”. Bottom right is a diagram shaped like a blue-to-purple connector between two areas. Above the left half is the heading “Hardware projects” and above the right half is the heading “Centers of Excellence (CoE)”. On the left half are a factory-like icon and the text “RISC-V” plus a small square logo with the text “epi”. Between the halves are four arrow labels pointing right: “Provide real use-cases”, “Discover performance issues”, “Evaluate app portability”, “Optimize app for RISC-V”. On the right half are multiple logos/text: “CHEESE”, “PLASMA PEPSC”, and a “CEEC” logo. Along the bottom of the flyer are thin decorative wavy lines.

As Europe accelerates its efforts in chip sovereignty, scientific applications need to be ported to and evaluated on emerging prototypes, assessing their performance as well as the technology readiness of the new hardware platforms. In this talk, we will share the experiences and lessons learned when porting applications from CEEC and other Centers of Excellence to the long-vector RISC-V accelerators from the EPI and EUPILOT projects across different domains and applications.
Attendees will learn code optimization techniques, common performance pitfalls, and evaluation methods for long-vector architectures, which they can apply to their own applications and code bases in order to improve performance on these novel hardware platforms.

Details

Venue

  • Online